Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology
Journal: International Journal of Science and Research (IJSR) (Vol.3, No. 7)Publication Date: 2014-07-05
Authors : Umashankar Dhepra; Rajkumar Gehlot;
Page : 764-767
Keywords : VLSI; CMOS; Full Adder; leakage current; process invariance and circuit invariance;
Abstract
Power consumption has emerged as a primary design constraint for today VLSI integrated circuits (ICs). AS per reducing Technology, mostly Nanometer technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU. In this paper we introduced low power consume one-bit full adders, including the most motivating of those are analyzed and compared for speed, leakage power, and leakage current. The simulation has been carried out on a Cadence environment virtuoso tool using a 0.45-m technology
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