Area and Delay Analysis of Modulo 2n plusmn 1 Adder Subtractor Using Prefix Adder on Weighted One and Diminished-1

Arithmetic architectures for modulo 2n+1 and 2n-1 adders and Subtractor are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n + 1 and 2n-1 addition. Second is Apart from addition a 2s compliment methodology has been introduced fro subtraction concept. The results are focusing on area and timing delay. These results is also being comparing in diminished-1 and weighted one for the individually adder and Sub-tractor and, while maintaining a high operation speed.