High Speed Implementation of Lifting Based Discrete Wavelet Transform (DWT) on FPGA

The objective of this project is to implement the high speed lifting-based two dimensional discrete wavelet transform (2D-DWT) algorithm on Field Programmable Gate Array (FPGA). The proposed method is based on new and fast lifting scheme with fully pipelined approach. Pipelining structure in DWT reduces hardware complexity and memory accesses and speeds up the performance. The conversion of raw image into Hex format is done using MATLAB and the Hex image is loaded into the FPGA kit. The result of the 2D-DWT provides four filtered images and is passed to display. The algorithm has been realized in Verilog HDL and implemented using XC6SLX16-CSG324C Xilinx Spartan-6 FPGA device. The currently available methods for calculating discrete wavelet transform (DWT) which is considered as conventional method of DWT requires lots of hardware (adders and multipliers). Such an implementation demands both a large number of computation and a large storage features that are not desirable for either high speed or low power image processing applications, so there is a need for calculating DWT in less amount of time with hardware minimization. Pipelined Lifting-Based DWT is one of such technique which is used to calculate DWT in fewer amounts of time and reduced hardware. The Lifting based DWT has wide areas of applications, among which medical imaging is most popular. It is used in image compression standards like JPEG, MPEG etc.