Design of Advanced Configurable Radix-4 Booth Multiplier for Low Power and High Speed Applications

Many multimedia and DSP applications are highly multiplication intensive so that the performance and power consumption of these systems are dominated by multipliers. The computation of the multipliers manipulates two input data to generate many partial products for subsequent addition operations, which in the CMOS circuit design requires many switching activities. Thus, switching activity within the functional unit requires for majority of power consumption and also increases delay. this approach dynamically detects the input range of multipliers and disables the switching operation of non effective ranges. Therefore, minimizing the switching activities can effectively reduce power dissipation and increase the speed of operation without impacting the circuits operational performance. Here attempt is made to combine configuration, partially guarded computation, and the truncation technique to design a high speed and powerefficient configurable BM (CBM). The main concerns are speed, power efficiency and structural flexibility. The proposed multiplier not only perform single 16-b, single 8-b, or twin parallel 8-b multiplication operations but also offer a flexible tradeoff between output accuracy and power consumption to achieve more power savings. Portable multimedia and digital signal processing (DSP) systems, which typically require flexible processing ability, low power consumption, and short design cycle, have become increasingly popular over the past few years.