Design and Simulation of SPI Master / Slave Using Verilog HDL

The object of this paper is to design and simulation of SPI (serial peripheral interface) master and slave using verilog HDL. The SPI (serial peripheral interface) is a kind of serial communication protocol. It transfers synchronous serial data in full duplex mode. The SPI is commonly used for communications between Integrated Circuits for communication with On-Board Peripherals. The SPI communicate in two modes master and slave. Where the master device generates serial clock and multiple slave devices are allowed with individual salve select lines. And the whole design is simulated and synthesized with Xilinx ISE design suite 13.2.