Design of FFT Processor for OFDM to Achieve High Efficiency Parameters

In the communication world of today more and more OFDM systems are brought on-line with an ever increasing number of standards, services, and applications, all with different requirements on the physical layer of the transceiver. The physical layer is frequent, due to power constraints and speed, implemented as an ASIC and thus locked to one specific case. Hence, the number of required implementations will grow fast. Due to this reason, there will be an interest from the industry�s point of view to search for a flexible architecture that can be configured to function with several standards, applications, or services. A flexible architecture will lead to re-usage of design and implementation and thus reduced cost. This document addresses both OFDM in theory and the implementation aspects of a flexible hardware solution for digital baseband OFDM. The FFT processor is a central part of an OFDM transceiver, and has been fabricated both as a standalone chip and as part of an OFDM transmitter chip. A scheme to reduce hardware and delay in an OFDM transceiver is proposed in this paper which can be significantly reduced with a cyclic suffix and a bidirectional FFT processor.