VHDL Implementation of Reed-Solomon Encoder-Decoder For WiMax Network

This article proposes, a system based on Reed-Solomon codec for WiMax networks. The proposed architecture implements various programmable primitive polynomials. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrical RS-coder-decoder. The implementation, written in a hardware description language (HDL), is based on an Berlekamp massey, Chien Search and Formey Algorithms. Wehave defined an advanced RS encoder-decoder architecture approach whichis a key solution for systems. Our approach is used inorder to implement on Xilinx a generic RS coder-decoder for WiMax networks. IEEE Std.802.16 specifies that the codec performs a variable number of check symbols in a codeword. The Reed-Solomon encoder has been checked for different error-correcting capabilities that is 4, 6, 8 etc. Reed-Solomon decoder synthesized using VHDL on Xilinx and simulated on ISE Simulator.The RS decoder implementation written in VHDL is based on Berlekamp Massey,Forney and Chien Search Algorithm. The performance of Reed-Solomon encoder RS (7,3)and,RS(15,9 ) is shown and Reed-Solomon decoder is checked for RS(7,3)and synthesizable on Xilinx and simulated on ISE Simulator. The performance are shown using two device Virtex 5 and Spartan 3e.