A Review on Reversible Logic Gate Multipliers

The efficient low power and small area multipliers in the digital circuits for the emerging technology are of more interest these days. Hence designing of the multipliers with the factors of low power, area and delay is dominant. For this purpose the reversible logic multipliers are designed in advantage over that of conventional multipliers. This paper describes the comparative analysis of different reversible logic gate multipliers in terms of number gates, number of garbage inputs, garbage outputs and quantum cost. Each of the multipliers operation can be generalized for NxN bit multiplication of their advantages.