Design of GDI Based Low Power and High-Speed CMOS Full Adder Circuits

Power consumption and delay are two important considerations for VLSI systems. The objective of this project is to reduce the power and to reduce the delay which increases the speed. Adders are very important components in many applications such as microprocessor and digital signal processing (DSP) architectures. Full Adder is one of the core elements. It used in many of the complex arithmetic logic circuits like multiplication, division, addition. In this paper Full Adder has been generated by the Gate Diffusion Input (GDI) technique. The proposed full adder is simulated with Tanner EDA using 0.18m CMOS Technology. By reducing the Transistor size, the power and delay are reduced. Simulation results show great improvement in terms of Power-Delay-Product (PDP).