A Survey on Analytical Delay Models for CMOS Inverter-Transmission Gate Structure

In this survey paper, a literature study on analytical delay models for a CMOS inverter and transmission gate has been done. Inverter followed by Transmission gate structure appears in many CMOS circuit design. Initially, the delay calculation of this entity is done considering them individually, which is not good. In this case, it does not account for the series stack effect that appears while driving a load through Inverter-Transmission Gate structures. But later on, advancements in this field of research resulted in considering the above said Inverter-Transmission Gate structure as a single entity in calculating the delay parameters or designing the delay model. This paper presents a review on the developments that occurred in designing an analytical delay model from considering the structure individually to treating it as a single entity. The recently proposed model considers the series stack effect along with the internal node voltage and parasitic capacitance, it also proposes a methodology to incorporate the effect of process-voltage-temperature variations and compared against SPICE simulation using 32nm Predictive Technology Modelling (PTM).