Ternary Logic Gates and Ternary SRAM Cell Implementation in VLSI
Journal: International Journal of Science and Research (IJSR) (Vol.3, No. 11)Publication Date: 2014-11-05
Authors : Punnam Nagaraju; Neerati Vishnuvardhan;
Page : 1920-1824
Keywords : Multiple-valued logic MVL; CMOS Ternary Logic; Ternary SRAM; Simple Ternary Inverter STI; Positive Ternary Inverter PTI; Negative Ternary Inverter NTI;
Abstract
: This paper presents Very Large Scale Integration (VLSI) design and simulation of a ternary logic gates and CMOS ternary SRAM cell. The Simple Ternary Inverter, Positive Ternary Inverter and Negative Ternary Inverter are designed in 180nm technology. The Ternary NAND Gate and Ternary NOR Gate are also designed and simulated. The ternary SRAM consists of crosscoupled ternary inverters. SPICE simulations confirmed that the functional behavior of the READ and WRITE operations is correct
Other Latest Articles
- Operating System: The Power of Android
- Human Gait Recognition Using Multisvm Classifier
- Design Transceiver for IEEE 802.15.4 using ZigBee Technology and Matlab/Simulink
- Enteric Fever Presenting As Diarrhoea and Thrombocytopenia: A Case Report
- A Study on CRM Practices in Apparel Retail Sector in Bangalore
Last modified: 2021-06-30 21:12:54