Design and Analysis of Low Power High Speed Area Efficient Multipliers using Compressors on FPGA

The main theme of the paper is to design Compressor Based Low Power high speed and Area Efficient Multipliers on FPGA. In order to perform higher order multiplications more number of adders are required for the partial product addition. Special kind of adders are introduced which are capable of adding five/six/seven/eight/nine bits per decade with which we can reduce the number of adders and these special kind of adders are called as compressors. In order to develop higher order compressors, the combination of XOR gates and MUX circuits along with the binary counter property is contrasted with the conventional design. By using these compressors we can reduce the vertical critical paths. In this paper we present efficient implementation of multipliers with compressors on FPGA. When compared to carry propagate adders (CPA), high speed compressors provide fast critical path, independent of bit width with practically no area overhead. Design of such compressors will reduce the stage delays, transistor count and power delay product (PDP) and the results are verified in SPARTAN 3 FPGA.