High Speed Convolution and Deconvolution Algorithm based on Ancient Indian Vedic Mathematics

In Digital Signal Processing, the convolution and deconvolution with a very long sequence is ubiquitous in many application areas. Both operation consume much of time. So our focus to develope more advance and simpler techniques. This paper presents a direct method of computing the discrete linear convolution, circular convolution and deconvolution. The most significant aspect of the proposed method is the development of a multiplier and divider architecture based on Ancient Indian Vedic Mathematics sutras Urdhvatriyagbhyam and Nikhilam algorithm. The implementation of linear convolution and circular convolution using vedic mathematics is functionally verified using Modelsim software and analyze on Altera FPGA platform using Quartus 2 software, parameter like area, speed and power will be compared to their implementation using conventional multiplier& divider architectures.