Design and Implementation of Parallel CRC for High Speed Application

High speed data transmission is the current scenario in networking environment. Cyclic redundancy check (CRC) is essential method for detecting error when the data is transmitted. With the challenging speed of transmitted data, to synchronize with speed, it is necessary to increase the speed of CRC generation. With the help of serial architecture a recursive formula is used from which a parallel design is derived which reconfigure rapidly to new polynomials. Usually the hardware implementation of linear feedback shift register used in serial crc generation does not achieve a high throughput, but is possible in parallel generation. The hardware scheme for computing the transition matrix of parallel cyclic redundancy checksum is used. This improves the polynomial adaptability. The factor of an area, required for a realization for storing the pre-computed matrix is also considered. The design lowers the area requirement. The equations allow the width of data to be processed in parallel and is selected independent of the degree of polynomial. The new design performs significantly in speed, area and energy efficiency. The derivation of the matrix necessary to set up all latches can be performed in software. Architecture uses the minimum number of clock cycles which increases the efficiency of the transmission process and easily adaptable to variation in transmission data bytes. The design architecture for CRC generation will be functionally verified using ModelSim and synthesized on Altera FPGA using Quartus 2 software.