FPGA Based Architecture for Radar Information Analysis

Radar is an object-detection system that uses radio waves to determine the range, altitude, direction, or speed of objects. The radar transmitter transmits pulses of radio waves or microwaves that bounce off any object in their path and the object returns a tiny part of the waves energy to the receiver. In the receiver it is processed to determine the presence of the target and location. Two main radar types are Continuous wave Doppler radar and Ultra wide band pulse Doppler radar. At the receiver part of Continuous Wave Doppler radar the incoming signal is initially converted to an intermediate frequency (IF) to filter out the unwanted low-frequency components, the filtered IF signal is then shifted to baseband using digital down converter (DDC) module. This paper emphasis on digital down conversion module at the receiver part. Digital down converter (DDC) consist of Direct Digital Synthesizer (DDS), parallel multipliers and a decimation filter. The Direct digital synthesizer produce sine and cosine waves whose magnitude is multiplied with a digital value from ADC in the parallel multiplier and the output from the multiplier is decimated to obtain the final Digital down converter output. The coding of digital down conversion module is done in VHDL and further it can be synthesized into FPGA. FPGA gives great flexibility, as compared to the conventional dedicated hardware components solution.