FPGA Design of Parallel Linear-Phase FIR Digital Filter Using Distributed Arithmetic Algorithm

Based on fast FIR algorithms (FFAs), we propose distributed arithmetic algorithm based new parallel FIR filter architectures, which are beneficial to symmetric convolutions in terms of the hardware cost. Multipliers are the major portions in hardware consumption for the parallel FIR filter implementation. The proposed new structures exploit the nature of symmetric coefficients of odd length and further reduce the amount of multipliers required at the expense of additional adders. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and post processing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter.