Modified Networks-in-Cache for Embedded Processor

A new cache architecture which utilizes the advantage of the tiling of cache Non Uniform Cache Architecture (NUCA) and the latency in accessing data from the tiles can be reduced by modified tag matching technique. Based on the fact that a memory system is said to be perfect if it can supply immediately any data that the CPU requests. The cache architectures pay an important role in how fast the data can be accessed from the cache by the processor. The proposed cache architecture consist of small and low latency tiles placed between different cache levels so as to reduce the inter cache latency gap between first level cache and secondary cache. The interconnection and routing of data through these tiles are done by three networks which expertise in separate cache operation so as to improve the performance. The tag matching technique presented in this brief for data protected with error correcting code is to reduce the latency and complexity. The practical error correcting code word is usually presented in a systematic form in which the data and parity parts are completely separated from each other so the advanced tag matching technique parallelizes the comparison of both parts. The incoming data matches the stored data only when a certain number of erroneous bits are corrected and a butterfly-formed weight accumulator is used for efficient Hamming Distance computing. The Verilog language is used for coding and simulated by using Model-Sim.