A Novel Low power and Area Efficient Carry-Lookahead Adder Using MOD-GDI Technique

Adders are given a fundamental importance in a wide variety of digital systems. Many improvements have been made to reduce the architectures of adders. The proposed method aims on Modified Gate diffusion input (MOD-GDI) which is a low power technique to design any digital system. This technique has been adopted from (GDI) Gate Diffusion Input - low power digital circuit design technique. The Mod-GDI technique which allows in reducing delay, power consumption and area of digital circuits, while maintaining functionality of logic design. This paper presents the Performance comparisons on low power techniques of basic combinational logic functions and to state that the proposed Modified Gate Diffusion Input logic (Mod-GDI) to be more power-efficient than the CMOS logic design. This paper also presents a novel structure of Carry-Lookahead Adder (CLA) using the primitive gates which are designed by MOD-GDI technique. This technique can be used to reduce the number of transistors compared to conventional CLA design. The design of the 8-bit CLA is primarily introduced and then the 16-bit CLA is followed. The designs are simulated using Mentor Graphics tool with a supply voltage of 1.8V at 90nm Process technology.