Fully Pipelined High Throughput Cost Effective FPGA Based Implementation of AES Algorithm

This proposes a fully pipelined high-throughput cost effective implementation of Advanced Encryption Standard (AES) supporting encryption and decryption with 128-, 192-, and 256-bit cipher key. AES is the most secure symmetric encryption technique that used for wireless communication. The AES based on the Rijndael Algorithm is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption. A high speed security algorithm is always necessary and important for wired/wireless communication. The symmetric block cipher key plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is advanced encryption standard (AES). FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. The design has been coded by Very high speed integrated circuit Hardware Descriptive Language. All the results are synthesized and simulated using Xilinx ISE and ModelSim software respectively. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput.