FIR Interpolation Filter for Multi-Standard Digital Up Converter Using FPGA

This paper proposes an implementation of pulse shaping FIR interpolation filter for digital up converter. The designing of root raised cosine FIR filter for multistandard DUC for different standards is reduces the multiplications and additions per input samples and reduction in the power consumption has also been achieved. The 2-bit binary common sub-expression (BCS) elimination method is used to design the multipliers so that the delay can be minimized with increased speed and power performance parameters. The design could be validated for a standard wireless communication technology with specific incoming bit streams. The proposed design could be implemented using RTL Code and functional correctness is verified using a sophisticated Modelsim/ISIM Simulator tool.