Low Power FPGA Architecture
Journal: International Journal of Science and Research (IJSR) (Vol.4, No. 6)Publication Date: 2015-06-05
Authors : Abhijeet Khandale; H R Bhagyalakshmi;
Page : 23-26
Keywords : FPGA; VTR; clock gating; CLB; ODIN II;
Abstract
A comprehensive analysis and implementation of FPGA architecture for low routing power and clock gated CLBs has been presented in this paper. The power consumption in FPGAs is more in routing and in clock network. As the FPGA has thousands of logic blocks and hard embedded micros spread across the FPGA chip, more numbers of routing lines and switch boxes are required. Also the clock network is built with same routing resources. The Configurable logic blocks with clock gating will allow reducing the dynamic power. The logical equivalence of CLB inputs will help to reduce the routing congestion and also improve the timing of the design.
Other Latest Articles
- The Impact of Firewall Security for Wireless Performance
- Modeling Kenya's Vulnerability to Climate Change ? A Multifactor Approach
- Fertility Desires of People Living With HIV in Enugu State Nigeria
- A Review of Captcha and Graphical Passwords to Enhance Security and Usability to Next Level
- Bio Conversion and Recycling of Zea Mays L Waste Implementing Bulking Agents and Dry Leaves for Leachate Control
Last modified: 2021-06-30 21:49:27