High Speed Vedic Multiplier Design Based On CSLA
Journal: International Journal of Science and Research (IJSR) (Vol.4, No. 6)Publication Date: 2015-06-05
Authors : Sijo Mathew; S. Chinnapparaj; D. Somasundareswari;
Page : 1068-1072
Keywords : Carry Select Adder; Urdhava Tiryakbhyam Sutra; Multiplier; Vedic Mathematics; Low power design;
Abstract
This work proposes an high speed Vedic Multiplier based on area, delay and power efficient Carry Select Adder. In this paper a fast method of multiplication based on ancient Indian Vedic mathematics is proposed. The whole of Vedic mathematics is based on 16 sutras and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. All the redundant logic operations present in the conventional CSLA are eliminated and proposed a new logic formulation for CSLA. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. The multiplier discussed here is compared with other multiplier to highlight the speed and power superiority of the vedic multiplier.
Other Latest Articles
- ICT Infrastructural Factors That Influence the Adoption of E-Learning in Public Secondary Schools in Kenya
- Melanotic Neuroectodermal Tumor of Infancy, A Rare Pediatric Tumor: Report of Two Cases with Review of the Literature
- Histological Analysis of Radicular Dental Calcifications According to the Size
- Eco-Friendly Synthesis and Characterization of Silver Nanoparticles Using Marine Macroalga Padina Tetrastromatica
- Histopathological Study of Soft Tissue Tumours (Three Years Study)
Last modified: 2021-06-30 21:49:27