Design and Implementation of Efficient FSM for AHB Master and Arbiter

Due to Moores law more and more amount of logic is being placed onto a single silicon die and it is driving the development of highly integrated SoC designs. So this high computational power must be matched with interconnect fabric which can handle it. There are many interconnect buses that are widely used in the industry like AMBA, Wishbone, Core Connect, Avalon etc. AMBA is most proffered among all of them because it has a hierarchy of buses with AHB (Advance high performance bus) can be connected to high performance peripherals and APB (Advance Peripheral Bus) that can be connected to low performance peripherals. Nowadays in industry development of Silicon on Chip (SOC) devices with reusable IP cores are given higher priority, the major challenge faced here is to ensure proper lossless communication between these IP cores in SOC device, this can be ensured with the help of standard communication protocols such as AMBA from ARM Ltd. In this paper we design and synthesize efficient Finite State Machine (FSM) for master and arbiter interface in AMBA AHB.