Design and Implementation of FIR filter using Carry Select Adder

Carry Select Adder (CSLA) is a basic building blocks used in data processing processor to carry out fast arithmetic functions. As a scale of integration keeps growing, signal processing systems is being implemented on a VLSI chip to a greater extent which demand not only high computation capacity but also consume large amount of energy. While performance and area remain to be the two major design parameters, power consumption is become a critical task in today-s VLSI system design. To reduce the power consumption of data processing processor we need to reduce number of transistors of the adder. So, there is a chance to reduce the power and delay in the CSLA structure. The proposed design uses D-latch instead of using RCA cascade structure for cin=1or cin=0. This CSLA is implemented in the adder of FIR filter. The proposed design achieves the two folded advantages in terms of delay and power.