Area Efficient architecture for 64 bit CSLA using Sum and Carry Generation Unit

Design of area efficient data path logic systems are one of the important areas of research to perform arithmetic operations in VLSI design there is a scope for reducing area. The CSLA architecture is simple to design and area-efficient. However, the computation speed is slow because each full-adder can only start operation till the previous carry-out signal is ready. Carry Select Adder (CSLA) is one of the fastest adders to perform arithmetic operations comparing all conventional adders. From the architecture of CSLA there is a scope for reducing the area and delay. Based on the modification of 8 bit, 16 bit, 32bit, and 64 bit Carry Select Adder (CSLA) architectures have been developed and compared with the existing CSLA architecture. A carry-select adder (CSLA) can be implemented by using Ripple carry adder. The proposed design 64-bit CSLA has reduced area as compared with the existing CSLA. Results obtained from proposed carry select adders are efficient in area. This proposed architecture has showed the performance of the proposed design in term of area. ISim simulator is used for simulating the CSLA and synthesized using Xilinx ISE design suit 14.7 and implementation proposed system on FPGA Spartan-6.