A Clock Gating Technique Using Auto Gated Flip Flop for Look Ahead Clock Gating

The look ahead clock gating based on auto gated flip flops method combines the previously three methods. Several techniques to reduce the power have been developed of which clock gating is predominant. This look ahead clock gating computes the clock enabling signals of each flip flop one cycle ahead of time, based on the present cycle data of those flip flops on which it depends. It avoids the tight timing constraints of auto gated and data driven by allotting a full clock cycle for the computation of the enabling signals and their propogation. A look ahead clock gating model is presented which is based on the auto gated flip flop. The comparison between the look ahead, data driven clock gating is done. The result shows the look ahead consumes 16nw while the data driven consumes 24nw power which is greater than the proposed look ahead clock gating. This clock gating is very useful for reducing the power consumed by digital systems. Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in international technology roadmap for semiconductor.