FPGA Implementation of MIL-STD-1553B Bus Protocol Controller for Aircrafts

Data buses are used in military applications to download information from the aircraft before launching of vehicle and coordinate information flow during the flight. Initially direct point-to-point wires were used to connect components in avionics systems. But when the complexity of the systems in the aircrafts began to increase, the wiring became both very complex and heavy. To overcome these difficulties, US Department of Defence published the 1553 serial data bus standard. MIL-STD-1553B is a widely popular, standard data bus that has been employed for data transmission in a variety of aerospace and defence systems. The entire control of the 1553 bus system is associated with in the Bus Controller (BC). The 1553B bus protocol controller is incorporated with a Manchester encoder and a Manchester decoder. In this work, protocol controller is implemented with the addition of other blocks such as protocol logic, arbitrator for meeting the demands of the protocol. The proposed system also incorporate memory management and processor interface logic. Here, the 1553B bus controller is modeled as a finite state machine in VHDL. Finally, all the components needed for the bus controller is integrated as a single block as a result area of utilization can be reduced. The proposed design is simulated in ModelSim and implemented onto a Xilinx based FPGA platform.