Improved Power Reduction and Aging Mitigation Using Gate Replacement and Voltage Scaling Techniques

As the VLSI technology and supply/threshold voltage continues scaling down, power consumption and aging are the major problems affecting circuit performance. The aging effect in circuits is due to the Negative Bias Temperature Instability (NBTI) which is a well-known reliability concern for PMOS transistors caused by the negatively biased gate voltages at high temperatures. In the meantime, reducing power consumption and aging optimization remains to be main design goals for almost all circuits. Major power dissipation is contributed by static as well as dynamic power. Static power is mainly deals with leakage power, which can be reduced by Gate replacement algorithms, which is one of the important standby mode internal node control technique. At the same time, aging effects are also optimized by this technique. In the other side, dynamic power consumption can be minimized by adopting multilevel voltage scaling technique. Applying a voltage scaling technique that changes the supply voltage of gates to a lower value in CMOS circuits is an effective way of reducing power consumption. In addition, this proposed method will compare with the existing power reduction techniques. Experimental results show that this method can effectively reduce the static, dynamic power leakages and circuit delay compared to previous techniques.