Design and Implementation of Content Addressable Memory (CAM) Architecture

Content addressable memory (CAM) is a storage memory with an extra comparison circuitry. It is also called as associative memory, which can be accessed by its own contents instead of addresses in a single clock cycle. Due to access of CAM in a parallel fashion, it has a high speed but consumes very high power. Also, an extra circuitry makes consumption of power higher. In this paper, a CAM architecture based on parity bit is proposed, which will reduce power consumption and increases its performance compared to traditional CAM architecture and other existing designs. Comparison of performance parameters of parity bit based PB-CAM with other existing architectures is presented here and Tanner EDA Tool under 130nm CMOS technology is used for implementation, simulation, and power and delay are estimated for performance evaluation of CAM architectures.