Design and Analysis of Dynamic Comparator with Reduced Power and Delay
Journal: International Journal of Science and Research (IJSR) (Vol.4, No. 11)Publication Date: 2015-11-05
Authors : Shashank Shekhar; S. R. P. Sinha;
Page : 1025-1029
Keywords : Preamplifier; Kickback noise; Dynamic Latch Comparator; Transmission Gate; Parasitic Node Capacitance;
Abstract
The need for low-power and high speed analog-to-digital converters is pushing toward the use of dynamic comparators to maximize speed and power efficiency. In this paper, performances of various types of the dynamic comparators are being compared in terms of speed, delay and power. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional comparator is modified for low-power and fast operation even in small supply voltages. It is shown that in the proposed dynamic comparator both the power consumption and delay time are reduced. The circuits are simulated using TANNER tool with 0.18m technology and supply voltage 1.8V.
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