Analysis of Design of Schmitt Trigger Based SRAM Cell Using a Novel Power Reduction Technique

In low power SRAM memory cell design Power dissipation through standby leakage and dynamic loss is a major problem. this paper is mainly based on low power cell operation and delay of SRAM designing this paper presents a novel technique to reduce short circuit power. The differential SRAM for ultra low voltage design for Schmitt trigger (ST) is analyzed using 180nm cmos technology. Schmitt trigger based differential SRAM cell design helps to sort the issues related to design problems in read and write operation of basic SRAM cell. Feed back is built in mechanism in proposed Schmitt trigger SRAM design. There is always trade-off among area, power and delay in any SRAM cell designing. In comparison to standard 6TSRAM cell the ST SRAM cell provides better read stability and having a high probability of read failure. Short circuit power dissipation isone of the considerable parameter in achieving low power. This paper mainly proposes a novel technique for achiving the low power consumption. Delay of an SRAM cell is maintained as it was without affecting the delay with the reduction of power. By using novel power reduction technique to reduce the short circuit power comparesd to the proposed design is reduced by 21 %. The aim of this project is to develop a circuit level technique that takes advantage of program behavior to reduce power consumption with no performance degradation. These simulations are implemented by the H-spice and synopsis tool.