Reducing Cache Energy in Embedded Processors Using Early Tag Access and Tag Overflow Buffer

Here we propose a new cache design architecture, where two techniques are combined together, one is tag overflow buffer and other is early tag access (ETA). This helps to improve the energy efficiency of data caches in embedded processors. The proposed technique performs the first technique using Tag Overflow Buffer (TOB) and only if a hit occurs the second technique Early Tag Access is performed. Thus only after an initial check for the content in TOB the actual ETA module is made active. The second technique called ETA is used to determine the destination ways of memory instructions much before the actual cache accesses. It, thus, enables only the destination way to be accessed if a hit occurs during the ETA. The proposed ETA cache method can be configured under two operation modes to exploit the trade offs between the energy efficiency and performance. It is shown that our technique is very effective in reducing the number of ways accessed during cache accesses. This enables to achieve significant energy reduction with negligible performance overheads. Simulation results demonstrate that, proposed ETA cache achieves over 52.8 % energy reduction on average in the L1 data cache and also in translation lookaside buffer. Compared with the existing cache design techniques, the ETA cache is very effective in energy reduction while maintaining better performance. And the proposed architecture with both TOB and ETA techniques together, have much better performance in terms of power reduction, delay minimization and area reduction. As a justification to above statement simulations using ModelSim and Xilinx are produced.