Weighted Random Pattern Generator by Using BIST

In Built-In Self-Test (BIST), test patterns are generated and applied to the circuit-under-test (CUT) by on-chip hardware, minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers (LFSR). A System-on-Chip (SoC) is the integration of all components of an electronic/computing system on a single integrated circuit. This paper presents a novel test pattern generation technique called BIST, As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at ion levels higher than the classical gate and register-transfer levels. This thesis deals with testing and design for testability of modern digital systems. This process is performed BY Pseudo-random testing is an attractive approach for BIST. A linear feedback shift register (LFSR) can be used to apply pseudo-random patterns to the CUT. An LFSR has a simple structure requiring small area overhead. Moreover, an LFSR can also be used as an output response analyzer thereby serving a dual purpose. BIST techniques such as circular BIST and BILBO registers make use of this advantage to reduce overhead. architectures, Results and Discussions Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum ****** of test patterns. The results also show that it reducing the testing effort for modern SoC deigns.