Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes

Low Density Parity Check (LDPC) technique is highly used in the communication protocol to effectively transfer data from transceiver end to receiver end. In this paper a highly efficient decoding technique viz. min-sum has used to transfer data. The data from the communication channel is used for the decoding process. Min-Sum algorithm decoder is implemented and simulation is done using Model sim. The hardware synthesis results are shown using Xilinx ISE 14.1 and Spartan 6 FPGA board.