An Efficient Architecture of Carry Select Adder Using Logic Formulation

A conventional Carry SeLect Adder (CSLA) consists of two Ripple Carry adders (RCA) and a multiplexer. It is used to generate two sum and carry words for both Cin=1 and Cin=0 and selects correct output sum and carry according to the input carry bit. The Carry Propagation Delay (CPD) is low but the area is high due to the use of 2-RCA unit. In the existing technique, the logic operation of CSLA can be performed by using Half Sum Generator (HSG), 2-Carry Generator (CG), Carry Selector (CS) and Full Sum Generator (FSG). It has less CPD but 2-CG unit increases the delay and area. In the proposed method, the CS unit is scheduled before the generation of carry words and hence the single CG unit is enough to calculate the final output carry. It results in reduction of area by 15 % and delay by 10 %.