VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers
Journal: International Journal of Science and Research (IJSR) (Vol.5, No. 3)Publication Date: 2016-03-05
Authors : L. Keerthana; M. Nisha Angeline;
Page : 983-987
Keywords : Numerical transformation; weight reduction; redundant technique; shift-and-add decomposition;
Abstract
In many digital systems, the most important and basic component ismultiplier and adder which are recommended for implementing the concepts of DSP systems, arithmetic and logic functions and multimedia applications. In many real time digital applications, power dissipation and hardware size are the major constraints. In this paper, we propose a method that combines a numerical transformation called number splitting with a shift-and-add decomposition scheme. In this design NxN bit multiplication is done by using (N-1) x (N-1) bit multiplication. The weight reduction and redundant techniques are used to greatly reduce the strength of multiplication. Various multiplier designs are taken and they are compared based on their speed and area. The speed of the system is increased by reducing the size of the hardware, power consumption and path delay. The designs are modeled using VHDL and implemented in Xilinx Spartan FPGA.
Other Latest Articles
- Application of Graph Theory in Electrical Network
- Cytochrome Oxidase Subunit I Gene Based Phylogenetic Description of Common Mormon Butterfly Papilio polytes (Lepidoptera: Papilionidae)
- Ethyl Methanesulphonate (EMS) Induced Mutagenic Disorders in Amaranthus tricolor L.
- Eddy Vertical Structure in Southern Java Indian Ocean: Identification using Automated Eddies Detection
- Expression of a Variant Chitinase Transcript of Helicoverpa armigera in E. coli
Last modified: 2021-07-01 14:32:41