Design of the Add Multiply Operator Using Modified Booth Recorder

Add Multiply operation it perform addition and result will be added to the input of multiplier. In proposed method s-mb recoder is used to the sum of two number in modified booth form. This technique implement the sum of two number in modified booth form. The sum to modified booth recoding it improve the performance of a different scheme of FAM unit. In existing method, Coventional design of the AM operator is implemented by using S-MB algorithm. The area, power dissipation and delay is increased by the use of adders. In proposed method, compressor adder is to be used instead of Carry select adder. The design is coded in VHDL and simulated in ModelSim and Synthesized in EDA tool Xilinx ISE9.2i. The power and delay will be reduced compare with existing methods