Parasitic Capacitance Extraction of 3-D DG-Finfet with Low K Symmetric Spacer Material

MOS devices are playing main role key in semiconductor industries. But The future limits on scaling of device is affected on MOS device. FinFET is most proposed device for nano scale industry. This technology is used beyond 50nm technology to reduce Short channel effect in MOS devices. It is designed with non-planner structure. Because of non-planar structure of FinFET parasitic capacitances (Gate oxide capacitance, overlap capacitance and fringe capacitance) makes adverse effect such as lower switching speed of device, making effect on access time, delay and Ion and Ioff of device. In this paper we proposed FinFET methodology to reduce parasitic fringe capacitance and overlap capacitance by optimizing gate side wall with low k dielectric spacer thickness and increase Ion to improve device driving capability. Threshold voltage also having impact of above parameters So device threshold voltage is reduced with low k spacer material i. e at least count of 0.0786v. The poly gate is used for front gate and back gate having work function of 4.65 to controls threshold voltage. Due to high k material leakage current increased but it is maintain using shorted dual gate technology. Our optimization in spacer material results in reducing total gate capacitance (123nF, 131nF and 123nF) and increases turn on time of device. Here 3d 20nm FinFET is design using TCAD tool (Silvaco) with monto Carlo technique.