Hardware ECG QRS Complex Detector in Low Power SoCs

This paper proposes a new hardware architecture implementing a low cost, energy efficient electrocardiograph (ECG) QRS complex detector. The proposed architecture can be used as an accelerator in an ultralow power System on Chip (SoC) which is the most important part of ECG devices. The architecture implements the modified version of MaMeMi filter algorithm [1]. The architecture is validated using the MIT-BIH Arrhythmia databases. More than 98.8 % of all QRS complexes were detected correctly by the architecture. The architecture is synthesized using 45nm CMOS technology and occupies the area of 0.23 mm2 and dissipates the total power of 1.26mW.