Comparison of Various Adder Designs in terms of Delay and Area

VLSI designers are constantly working towards the optimization of speed, power, and area of circuits, but practically it is difficult to optimize all at the same time. This paper presents a comparative study of the designs of parallel adders- ripple carry adder, carry look-ahead adder and Kogge-Stone adder, which have been designed using Xilinx ISE 14.7 Design Suite and synthesized for Spartan 3 FPGA. All the adders have been designed for 4-bit, 8-bit, and 16-bit operands and a comparison of delay performance and area utilization has been made as per the data obtained from the synthesis results. The effect of parallelism on speed and area of adder designs has been analysed, and it has been observed that both the parameters cannot be optimized at the same time. If parallelism is increased in order to increase the speed of operation, then it will result in large area occupancy, and if area is to be optimized then we have to adjust with the slow speed of system.