Test Pattern Generation for Integrated Circuit Test Using Distance between Vectors

Random testing is a well-known concept that requires that each test is selected randomly regardless of the test previously applied. In actual practice it takes the form of pseudo-random testing. A well-known method for generating test vector is pseudo-random number generator which is based on LFSR. Recently the anti-random sequence has attained attraction and shown to have better statistical properties compared to pseudo-random numbers. In antirandom testing, in the previous researches, the test vector are generated by using the hamming or Cartesian distance techniques and in the random testing, the test vector are pseudorandom numbers generated in the MATLAB (1). This research aims to develop a test pattern generation (TPG) algorithm using black box and possible with some deterministic approach which could produce comparable fault coverage compared to some of well known TPG methods such as random and anti random, one other purpose of this research to a achieve high fault coverage using less number of test vector with maximum distance. Fault coverage of two test vector is related to the distance between them, two input vector with large distance between them can give greater number of fault detected. The work will be heavily based on understanding and analyzing the effect of test vector distance from one another and fault coverage. The development tools that will be utilized in this research would be Matlab and Atalanta fault simulator.