Design and Analysis of Full Adder Using Adiabatic Logic

Power dissipation is an increasing concern in VLSI circuits. New logic circuits have been developed to meet these power requirements. Power dissipation can be minimized by using various adiabatic logic circuits. In this paper an Adder circuit has been proposed based on 2PASCL and ECRL logic and then compared with Positive Feedback Adiabatic Logic (PFAL), Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison shows significant power saving.