Design and Analysis of f2g Gate using Adiabatic Technique

This paper presents the comparison of conventional and two efficient adiabatic logics ECRL and PFAL. F2G gate is implemented using these two design technique. F2G gates are reversible gates. Reversible computing performed on F2G gates with adiabatic design techniques promises more reduced in power consumption as compared to traditional adiabatic CMOS circuits. Comparison in this paper shows very encouraging results in terms of average power consumption, transistor count. The designs are simulated and implemented on Cadence ICE6.1.5 virtuoso Design Environment using UMC 180 nm transistor model. The simulation results indicate that ECRL is better than PFAL, adiabatic logic at lower value load capacitancein terms of average power consumption and transistor count for implementation of F2G gates at low frequency andlow power application.