DMC Based Router Architecture for Dynamic Network on Chip

Network on Chip is the most viable solution for establishing communication among various modules in a System on Chip. A modified Error correction and detection mechanism is proposed in this paper which is applicable for the Dynamic Network on Chip. In DyNoC, the position and the number of components may vary during runtime The architecture of an such an NoC router is considered and significant modifications are made in the error detection and correction regime. The architecture is modelled using VHDL in Xilinx ISE Design Suite 13.2.