Design and Analysis of Advanced Booth Dadda Multiplier Using Approximate Compressors

Processors processes on the basis of arithmetic operations. Among the basic arithmetic operations, the most complex is the multiplication as it consumes more time for generation of partial products. So a faster multiplier is required to speed up the processor. A faster multiplier can be accomplished by the reduction of partial products. Here in this paper, Radix 4 booth algorithm is used for partial product reduction and Dadda multiplier is used to reduce the number of adders. This multiplier can be called as Advanced Booth Dadda Multiplier as two methods are clubbed together for different operations. Approximate compressors are utilized in the reduced partial products to minimize the delay and no. of transistors. Two different designs for utilizing the proposed approximate compressors are proposed and analyzed for Booth Dadda Multiplier. Detailed simulation results are provided. The utilization of proposed approximate compressors in Dadda Multiplier and its use in advanced Booth Dadda Multiplier is analyzed and is compared with the normal multiplier. The results show that there is a significant reduction in the delay and number of transistors when compared with the normal multiplier.