Fusion of March Algorithms in Counter based BIST for the Detection of Faults in RAM

Embedded memories covers the major portion and are the inevitable part of many of the SoC solutions. They are most sensitive to faults due to the dense design. . A wide variety of faults can occur, causing various failures in the memory functions. Component density, Circuit layout, Manufacturing methods are some of the sources of the occurrence of the faults in the memories. Built-in self-test (BIST) mechanism has widely been used to test memories like RAMs, since it reduces the test cycle duration and the complexity. A counter-based BIST architecture is used here. Several algorithms of different complexities are developed to test RAMs. Among them, March algorithms were considered as the simple and widely used ones. It consist of sequences of read and write operations for the detection of faults. Fusion of March algorithms like MATS, March C and March X are used in this work for the detection of Stuck-at fault, Coupling fault and Transition fault respectively. Detection of different faults in a RAM memory using a single counter based BIST design is advantageous. Selection of the March algorithm is based upon a mode selection switch. Compression of the test data is carried out using a decoder module. The fusion of the test algorithms optimizes the performance of the BIST Controller. Detection of different faults in a RAM memory using a single counter based BIST design is advantageous. Compressed test data is obtained in the simulation result, using a decoder module. The design of the Counter-based BIST module reduces the area overhead and complexity compared to that of the FSM-based design The implementations are carried out by using Verilog hardware description language and Xilinx ISE 13.2. The proposed method reduces the fault detection time as well as the tester storage requirement.