Ultra Low Power Design of Combinational Logic Circuits

The dynamic power utilization of CMOS circuits is constantly turning into a noteworthy worry in Very Large Scale Integration design. This issue can be fathomed with the assistance of adiabatic method that diminishes the dynamic power utilization in the pull up network and the energy stored on the load capacitance can be recycled. A multiplexer is the essential part of the any digital circuit and a standout amongst the most used circuits. An assortment of uses a multiplexer has, where a multiplexer can be actualized for e. g. in Full Adder, Arithmetic Logic Unit (ALU), Digital Compressor and so on. This paper displays the semi adiabatic Modified Positive Feedback Adiabatic Logic (MPFAL) for low power operation through energy recovery procedure. The circuit of positive Feedback adiabatic (PFAL) inverter has been modified. Correlation with static CMOS and PFAL circuits are made to demonstrate the designs. In post-layout simulation, energy saving funds of 27 % is accomplished against the Modified PFAL Inverter, NAND, NOR gates and multiplexer circuits. The different change results are analyzed in mentor graphics.