LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN WITH CONDITIONAL PULSE-ENHANCEMENT SCHEME

With the growing uses of moveable and wireless electronic systems, reduction in power consumption has become additional and additional necessary in today’s VLSI circuits. Over the past decade, power consumption of VLSI chips has perpetually been increasing. Moore's Law drives VLSI technology to continuous will increase in semiconductor unit densities and better clock frequencies. The trends in VLSI technology scaling within the previous couple of years show that the amount of on-chip transistors increase regarding four-hundredth each year. And operation frequency of VLSI systems will increase regarding half-hour each year. though capacitances and provide voltages scale down meantime, power consumption of the VLSI chips is increasing unceasingly. In CMOS digital circuits, power dissipation consists of dynamic and static parts. Since dynamic power is proportional to the sq. of provide voltage VDD, lowering provide voltage is that the best thanks to scale back power consumptions as long as dynamic power is dominant. With the lowering of provide voltage, semiconductor unit threshold voltage ought to even be scaled so as to satisfy the performance necessities. sadly, such scaling will result in a dramatic increase in leak current, that become a vital concern in low voltage and high performance circuits. For consecutive circuits, there area unit many technologies to scale back their leak power. MTCMOS, leak feedback, gate-length biasing, and DTCMOS are applied in flipflops. MTCMOS technology provides low leak and high performance operation by utilizing high speed and low VT transistors for logic cells and low leak and high VT devices as sleep transistors