FPGA Implementation of a Image Encryption System using AES Algorithm

Digital image typically has to be keep and processed in an encrypted format to take care of security and privacy. For the aim of content notation and/or meddling detection, it's necessary to perform data concealment in these encrypted images. During this approach, data concealment in encrypted domain while not decryption preserves the confidentiality of the content. Additionally, it's a lot of efficient while not decryption followed by data concealment and re-encryption. In this paper we tend to implement the image encryption system using AES encryption and decryption algorithmic program. This algorithmic program was implemented using micro blaze Processor on Spartan3EDK (XC3S200) FPGA in Hardware and software co-design environment using Xilinx platform studio and synthesis results show that area consumption is low.