Study and Implementation of Physical Layer Coding Used In Super Speed USB

This paper implements the DC balanced 8B/10B coding in Super speed USB which employ a very fast FPGA from Xilinx family is proposed. This technique can be used by other high speed serial buses such as PCI Express, IEEE 1394b, Serial ATA, SAS, Fiber Channel, Gigabit Ethernet, Serial Rapid IO and HDMI (Transition Minimized Differential Signalling) that use the same coding. Using the look-up table and memory with fast technique made this design efficient to be implemented. Moreover, the proposed method has very low complexity and fast to execute with minimum logic and also easy to implement. The Scrambling and descrambling modules are added in the above modules to support USB 3 physical layer transactions.